Frequently Asked Questions

Welcome to our FAQ. If you need help with a question you don’t find here, contact us—we’ll be delighted to help you in any way we can.


Getting Started

Programming FPGAs

Design Flows

Getting Started

  • How do we get started with your system?

    All Pico hardware comes with an installer file. Simply print out the “getting started” file and follow the directions. This includes a set of C++ API source files; one of which is PicoDrv which represents an FPGA.
  • How do I interface with a host processor?

    Pico Computing HPC systems are designed to be easily interfaced with standard CPU host systems through their PCIe bus.
  • How do I interface to more than one module?

    Pico provides a Verilog framework that gives you access to all basic functionality of the FPGA system, whether this is one module or up to 48 modules. The Pico software API includes a source file called PicoDrv which creates a PicoDrv object for each FPGA module in a system. Interfacing to Pico FPGA modules is as simple as interfacing via PicoDrv.

Programming FPGAs

  • How do we program an FPGA in your system?

    The Pico Framework provides access to all of the basic functionality of the FPGAs in your system. When you build a configuration file for an FPGA, the Pico framework will be the toplevel and your module will be instantiated inside the framework. You create a PicoDrv object for each FPGA in the system.
  • What is the loading mechanism for backplane-mounted modules versus the standalone/embedded modules?

    Programming a Pico Computing module is accomplished via the PCIe bus or a JTAG header, depending on whether it’s an embedded or HPC application. Our standalone modules use Samtec headers. We can also design and build a custom expansion header for you or provide schematics, from which you can design your own.

    Loading for backplanes is via PCIe. There is a on our EX-400 & EX-500 backplanes, for example, include a Spartan-6 FPGA that we use to load the module FPGAs. Invoking our driver loading functions is all one needs to do. However, for embedded modules, since there is not likely to be another FPGA on the carrier board, loading is from configuration FLASH only. We provide a loading mechanism that does not require a Xilinx red box and cable. We provide API calls to load FPGAs. Our backplane (EX-400 or EX-500) is not required, however; the backplane does provide a means for FPGA loading from the host. If run in standalone, then your bit file will have to be programed onto the configuration FLASH, which will then load the FPGA. We also support and provide examples of DMA transfers through PCIe.

Design Flows

  • How does Pico Computing work with Xilinx tools?

    Pico Computing firmware (for FPGA designs) is fully compatible with Xilinx’s ISE environment. Because of the difficult nuances of configuring an ISE project, we distribute a collection of ready-to-go ISE projects. To start your own project, simply find the sample that best matches your communication model and Pico Computing module/board, and copy it to your work directory. The copy function will provide all source files for the Pico Computing Framework so you just need to add your own code.

  • What simulators does Pico Computing you support?

    We currently support both the Xilinx ISim and the Altera ModelSim (Mentor’s simulator) simulators.
  • How do I recompile my existing code to run on Pico Computing products?

    Existing code written for serial processors should not be recompiled to run on parallel FPGA architectures, as the many parallel benefits of the FPGA would not be realized. In fact, FPGAs are clocked much slower than CPUs (a significant power consumption benefit), so serial code would run even slower. Existing code should be analyzed to discern where the parallel nature of FPGAs offers the largest benefits, and only that part of the code should be rewritten to take advantage of the parallel nature of FPGAs. In this way, the biggest benefit is reached with the smallest effort.